1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory, and more particularly to a nonvolatile semiconductor memory in which data lines are electrically connected via select transistors to one end of a memory string where a plurality of memory cells are electrically connected in series.
2. Description of the Related Art
Nonvolatile semiconductor memories or NAND type flash memories are under development, since they can electrically erase data and have a large memory capacity. The NAND type flash memory includes a memory cell array in which memory cell units are regularly arranged. Source lines and data lines are connected to opposite ends of the memory cell units.
Each memory cell unit includes a memory string to which a plurality of memory cells are electrically connected; a source selecting transistor electrically connected to one end of the memory string; and a drain selecting transistor electrically connected to the other end of the memory string. A source line is connected to a source region of the source selecting transistor. For instance, a common signal line is connected to a gate electrode. The data lines are connected to a drain region of the drain selecting transistor, and a drain selecting line (drain selecting gate line) is connected to the gate electrode. Each memory cell connected to the memory string is constituted by a transistor having a charge accumulating region. Word lines are connected to the gate electrode of the foregoing transistor. Charges serving as data are accumulated in the charge accumulating region.
In the nonvolatile semiconductor memory, the word lines extend across the memory cells, are regularly spaced similarly to the memory cells, and are connected to opposite ends of the memory string. The data lines extend along the word lines, and are regularly spaced similarly to the memory cell units. The source selecting signal lines are adjacent to and extend along the word lines. The drain selecting signal lines are adjacent to and extend along the word lines. The source selecting signal lines and the drain selecting signal lines are present on a conductive layer of the word lines, and are made of a gate material same as that of the word lines. Specifically, a gate material which can withstand a high temperature in a manufacturing process is used.
Japanese Patent Laid-Open Publication No. 2002-299478 describes one example of such NAND type flash memories.
The following problems are conceivable in the foregoing NAND type flash memories. As NAND type flash memories are being modified to have a large memory capacity, memory cells have to be downsized. The more extensively memory cells are shrunk, the smaller a line-and-space size. This leads to a reduced wiring width of the drain selecting signal lines. Therefore, the drain selecting signal lines tend to have large resistances, which inevitably reduces data reading speeds.
Further, as the memory cells are downsized, a width of the memory cell units and a space between the memory cell units tend to be reduced. This would lead to a reduced wiring width of the data lines. Therefore, the data lines tend to have a large resistance, and the data reading speed will be slowed down.